Annual report 2000

• Introduction
• Staff
• Graduate education
• Undergraduate education
• Research
• Publications

Introduction

In the following annual report, research and teaching activities during 2000 will be described. Outside research and teaching, a major event in 2000 was when Christer Svensson donated art to the department. Four windows, depicting silicon atoms and silicon chips, by artist Monica Sand have been mounted in the corridors of the Electronic Devices division.

In the end of 2000, 21 people, of which twelve are graduate students, are engaged in research and teaching. Additionally, four external graduate students (not employed at the group) are engaged.

Staff (Dec. 31, 2000)

Professor

Christer Svensson

Professor

Per Larsson-Edefors

Secretary

Anna Folkeson

Associate Professor

Dake Liu

Adjunct professor

Staffan Rudner

Adjunct professor

Aziz Ouacha

Senior Researcher

Quamar ul Wahab

Guest Researcher

Jan-Erik Eklund

Christer Jansson

Senior Research Engineer

Arta Alvandpour

Graduate students

Håkan Bengtson

Mattias Duppils

Daniel Eckerbert

Henrik Eriksson

Kalle Folkesson

Tomas Henriksson

Darius Jakonis

Robert Malmqvist

Ulf Nordqvist

Mikael Olausson

Annika Rantzer

Daniel Wiklund

External graduate students

Rolf Johnsson

Ulf Ringh

Joakim Strömberg

Ingemar Söderqvist

Graduate education

We have had one course for PhD students during 2000: Per Larsson-Edefors gave Electronic Design Automation for Physical Design, 5 credits.

Undergraduate education

Christer Svensson was appointed responsible for the Socware branch of study in the Y and D programs. The Socware branch of study is the result of a national initiative, to promote System-on-Chip education and research at three universities. Per Larsson-Edefors has been responsible for the Physical Electronics branch of study in the Y program.

Research

High-Performance Front-Ends (Svensson, Rudner)

Low-Power High-Performance VLSI Design (Larsson-Edefors)

Neutron-Induced Soft Errors in Electronics (Svensson)

The Next Generation System-on-Chip (Liu)

Christer Svensson has served in the program committees of the European Solid-State Circuits Conference (ESSCIRC) 2000 and the International Solid-State Circuits Conference (ISSCC) 2001 (European subcommittee). Per Larsson-Edefors served in the program committee of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2000. Christer Svensson is elected member of the IEEE Solid-State Circuits Society Administrative Committee. Per Larsson-Edefors is elected board member of the Dept. of Physics and Measurement Technology.

Christer Svensson returned from a sabbatical at Intel Corp., Hillsboro, USA, in March 2000. Per Larsson-Edefors was acting head of the division in Christer Svensson's absence. Furthermore, Per Larsson-Edefors was Visiting Professor at Intel Corp. during the summer of 2000 and Daniel Eckerbert is on a 6-month Internship at Intel Corp. as of Nov. 2000.

In summary, during 2000 the group has published 14 journal papers and 26 papers in national and international conferences. One patent application has been filed.

High-Performance Front-Ends (Svensson, Rudner)

Analog-to-Digital Converters [5], [15], [33]

(J-E Eklund, K Folkesson, D Jakonis and C Svensson; J Elbornsson and F Gustafsson [Communication Systems, Dept of Electrical Engineering])

High-performance Analog-to-Digital (AD) converters are one of the key elements in radio, radar and modem transceivers. High resolution, high speed and low distortion are essential characteristics. We strive to improve the AD converter along four lines; improved understanding of basic limitations, improved models including modeling of errors, removal of errors through better circuit techniques and removal of deterministic errors through adaptive error correction.

A Matlab-based AD converter model has been developed. Existing experimental AD converters (designed earlier in the group or by Ericsson Microelectronics) are measured and modeled. One result is the successful modeling of dynamic errors occurring at high sampling frequencies. These AD converters also exhibit matching errors. We have developed and tested some algorithms for adaptive correction of matching errors. The adaptivity means that error identification is performed during normal operation, and the identified errors are then used to correct the data. We have analyzed basic limitations to AD conversion and found that the most critical issue seems to be sampling jitter, which sets a large noise floor in the presence of a strong, disturbing signal. As a result of this, we initiated the design of a "jitter-free" sampler, with small non-linear errors, in CMOS. In a next step, we aim at developing an interleaving minimum jitter sampler for applications in broad-band soft radios.

The AD converter work is performed in cooperation with Ericsson Microelectronics, the Swedish Defence Research Establishment (FOA), and the division of Communication Systems, Dept. of Electrical Engineering.

New Circuit Architectures for Radio Frequency [38], [39], [40]

(R Malmqvist, A Ouacha, S Rudner and C Svensson)

Active narrow band microwave integrated filters with sufficiently good filter performance in terms of high gain together with low noise, low inter-modulation distortion and low temperature sensitivity may facilitate the realization of highly integrated receivers in future adaptive radar systems. During 2000 we have investigated a novel balanced second-order recursive filter topology. The filter consists of two identical second order filters placed between two quadrature couplers. The second-order filters consist of a tunable recursive active low-noise filter in cascade with a tunable recursive filter with good inter-modulation properties. The simulations indicate that this filter design can achieve a performance adequate for the on-chip microwave receivers of future adaptive radar antennas. A tunable X-band MMIC filter based on this topology has also been designed and will be fabricated by OMMIC using a 0.2-um GaAs/AlGaAs PHEMT based MMIC process. This work is performed in close cooperation with the Swedish Defence Research Establishment (FOA).

Mixed Analog/Digital Signal Processing [29], [45]

(M Duppils, J-E Eklund, C Svensson)

Front-end electronics normally include signal processing in both the analog and the digital domain, with an AD converter in between. In a sampled data system, there is some degree of freedom to choose to process data in the digital or the analog domain. An optimum choice should save power and hardware in the analog and the digital parts as well as in the AD converter part. We are investigating how to utilize a new mixed analog-digital multiply-accumulate unit to move some signal processing tasks from the digital domain to the analog domain. For narrow-band systems, filter operation is integrated into the sampling operation. This filter performs the channel selection and the decimation before the AD conversion takes place. Thus, the cost of AD conversion is reduced and power is saved. The results have been verified by chip measurements. We are also investigating how to perform the WCDMA correlation function before AD conversion.

I/O Circuits for Gigabit Rate Opto-Interfaces and Chip-to-Chip Communication [28]

(H Bengtson and C Svensson)

The ultimate limit for the data rate between chips is given by the properties of the transport medium, in this case the printed circuit board. We have therefore developed a new time domain model for printed circuit boards, which allow accurate analysis of signal transfer and accurate prediction of maximum data rates (this work was performed at Intel Corp., OR, USA). Further studies will include receiver architectures for very high data rates between chips (~10 Gb/s).

Another application for high-speed interfaces occurs in connection to the fast-developing fiber communication. We have initiated a study of the possibility to integrate the photodiode interface in CMOS, including transimpedance preamplifier, sampling, phase extraction and equalization.

High-Frequency Wide-Bandgap Semiconductor Power Devices [6], [36], [43]

(R Johnsson, Q Wahab, S Rudner and C Svensson)

The combination of several advantageous material properties such as high electric breakdown field and high saturation velocity makes SiC and GaN promising materials for high power microwave transistors. The high thermal conductivity of SiC also makes it an ideal substrate material for these transistors. Theoretical calculations indicate that SiC MESFETs and GaN based HEMTs could have output power densities a factor of 5-10 higher than those of standard technologies. During 2000 the performance of SiC MESFETs, fabricated on a structure with non-constant doping profiles in the channel and buffer layers have been studied in detail. A very good correspondence between experimental DC-characteristics and physical simulations was obtained, when using the doping profiles from SIMS measurements. The non-linear simulation effort is approached in two different ways. The first is to fit the Chalmers model for GaAs FETs/HEMTs to SiC MESFET characteristics and extract the modified parameters for the modeling of measured and modeled SiC MESFETs. This model could then be used as support for amplifier design and to gain knowledge of the influence of the non-linearities and high power operation on the transistor. In a second approach we are using a time domain modeling in the circuit simulator module of Medici to model the non-linear characteristics of the transistor.

Low-Power High-Performance VLSI Design (Larsson-Edefors)

The VLSI research group has been active since April 1 1997 when, then, Assistant Professor Per Larsson-Edefors returned from a post-doc period at National Microelectronic Research Centre (NMRC), Ireland. At the present time the group is active in research on circuit and physical design, with emphasis on low-power and high-performance circuits as well as performance estimation techniques.

An obvious driving force behind electronics consuming minute amount of power is identified in portable products, carrying huge values and future prospects of growth. Less known to the public is the necessity to reduce or at least actively control power dissipation in microchips, as the trend clearly indicates the power consumption is the factor that can break the trend towards further integration. Leaving the rigorous technical discussion to the sections below, we can observe that the general conclusion today is that power will have impact either on clock rates, integration densities or die (chip) sizes. Among design trade-offs are e.g. shifts of balance between high-performance and medium-performance circuit portions, by the use of multiple threshold voltages. The choice of balance is clearly delicate, as we cannot sacrifice performance for reduced power.

The primary goals for the present project are the following:

• to study the prospects of low-power high-performance techniques for CMOS circuits, especially in a certain number of critical applications such as datapath components
• to study and develop estimation techniques, both algorithms and models, for performance parameters such as power consumption
• to research the possibilities to find high-performance circuit techniques with acceptable power consumption for future fabrication processes

Circuit-True Power Estimation [14], [31]

(D Eckerbert, H Eriksson, P Larsson-Edefors)

The dominant source of power consumption in digital CMOS circuits is the switching power, which is caused by periodic charging and discharging of nodal capacitances. Traditionally this source has been viewed as the only source of power, probably owing to the fact that it is fairly easily described and fairly readily included in EDA strategies. Furthermore, models of switching power, in order to master the complexity of implementation, have been based on very simplified parameters. Since some of the earlier neglected phenomena constitute a fraction of power consumption, which increases continuously, considerations which have been made in the past are no longer suitable. In this project the main goal is to thoroughly investigate and model the "forgotten" circuit-level phenomena, which cause conventional power estimation values to deviate significantly from the true power. An additional incentive for this research is that this deviation will be even more pronounced in future CMOS processes.

The phenomena of particular interest are short circuits, Miller (mutual) capacitances, undesired signal transitions (glitches) and leakage currents. However, complications arise from the fact that all phenomena are related, and thus a clear description of one implies certain fuzzyness in defining another. The goal of creating both understanding and estimation methods has been accomplished in several critical domains. Recently, in 2000, we have analyzed and described how glitches, and their contribution to power consumption, depend on supply voltage [31] and we have worked on defining leakage definitions for CMOS gates [14].

RTL Power Estimation [15], [27]

(D Eckerbert, P Larsson-Edefors)

An important step towards achieving low-power electronics solutions is to make power estimations available to designers as early as possible in the design process. At a behavioral level, very few things are known about the final, physical implementation. Still, this is the level at which the designer makes a comprehensive survey of possible design options. To be able to evaluate the design options, a structural correspondence to the behavioral description is created and this structure often is situated at the RT-level.

Traditionally the RTL components have been in focus, whereas interconnects and their impact on power consumption has been poorly investigated. Results of this project include the development of a design-sensitive wire-length estimator [27], where individual wires can be identified and estimated for length although the input data to the estimator is abstract and contains no implementation information.

When running simulations at RT-level, almost only input and output signals are available. A viable model for the power consumption is the linear regression model, where transitions at the inputs and outputs are weighed against power consumption. To improve the precision of this model, the input/output vectors are stratified into several classes, each of which has its own set of power consumption parameters. Currently in this project, methods for using the linear regression model in the context of deep submicron fabrication technology are investigated. One key issue is the introduction of physical interaction between RTL components, by the notion of physical interconnections [15], and another is the inclusion of leakage current in the RTL component, which is difficult as leakage is complicated to model at higher levels of abstraction [14].

Low-Power High-Performance CMOS [7], [18], [19], [30], [41]

(D Eckerbert, H Eriksson, P Larsson-Edefors)

Design of low-power high-performance CMOS circuits is significantly facilitated when the designer has a thorough understanding of all attributes of power consumption. Not only is it possible to find power-efficient solutions in a quick manner, but the implementations have the potential to be power optimal in its true sense.

At application level we have during 2000 had the following sub projects running:

• One sub project, which is not finished yet, comprises a low-power high-performance DFT processor. A sub set of the processor, including a full processing element, has been designed and fabricated in a 0.35-um CMOS process. This design project has the explicit goal of combining a number of power-saving design methods within a novel implementation structure [41].
• Low-power implementations targeted for FPGAs is the second project in 2000. Here, the experience in circuit design has aided us in reconfiguring an FPGA, such that power can be reduced. The power-reduction technique is based on a transformation of arithmetic implementations into bit-interleaved structures, for which SRAM cells can be used as storage elements [30].

At circuit level we have been active in three different sub projects:

• A very power consuming part of large chips is long interconnects or buses. A study on repeater insertion in long interconnects for maximal throughput was conducted [7].
• Datapath components are key to all electronics design, and pose design difficulties as they require a tight inter-relation between the algorithm of the operation and the circuit structure to function efficiently. We are currently investigating new circuit and micro-architecture solutions in parallel adders and multipliers. By using a new transistor solution for a Manchester carry chain, we have been able to design and fabricate a power efficient 0.35-um 32-b adder with a delay of 2.8 ns [19]. In parallel multipliers so far only the final addition of the outputs of the partial product reduction tree can be done using a carry-propagate adder (CPA). Since the CPA is the fastest possible adder, we have studied how to design an efficient multiplier (in terms of power and performance) which contains only CPAs as building blocks [18].

Neutron-Induced Soft Errors in Electronics (Svensson)

(P Hazucha, K Johansson, C Svensson)[3], [4], [20], [21], [46]

Integrated circuits continue to improve at a very high pace. The strongest factor in this development is the downscaling of geometry and supply voltage, which has been going on since the 60s. In order to predict and understand the future developments in the field, it is essential to understand the physical limits to downscaling. One of the least understood limits to downscaling is the increased error rate caused by natural cosmic radiation. We therefore initiated a study of these effects in collaboration with Ericsson-Saab Avionics, and Intel Corp.

The dominating cosmic radiation in the atmosphere (including ground) is neutron radiation. The neutron flux gives rise to so-called single event upsets, or soft errors, in electronics. As the stored charge in each logical node decreases with decreased dimensions and voltage, the soft error rate will increase. Our objective is to develop methods for the investigation and prediction of these phenomena.

We have performed measurements on real chips in environments with high neutron flux, at high altitudes (in airplanes) and in artificial neutron flux (The Svedberg Laboratory in Uppsala and Los Alamos Laboratories in New Mexico). We also developed a special test chip for a systematic characterization of the fabrication process and performed process characterization of single event and multiple events upsets with this chip. Finally, we have used our results to predict the soft error rates of fabrication processes a few generations ahead.

The Next Generation System-on-Chip (Liu)

This project focuses on research of multiple heterogeneous digital signal and protocol processors as well as the multiple processor integration technology for system-on-chip (SoC) integration. The research area is allocated in computer architecture and functional VLSI design. The project follows the activity of the SoC cluster proposed by the Swedish government.

The project is divided into three sub projects:

Protocol Processor for Network Terminals [22], [23], [34], [35], [42]

(T Henriksson, U Nordqvist, D Liu)

The network is developing very fast and new applications are emerging everywhere. We noticed that the network system and SW research is going on so fast that it almost left the HW research lagging behind. The current available protocol processors are either ASICs, having no flexibility, or RISC based, having lower performance. This project aims to bridge the gap between ASIC and RISC, and to demonstrate a unique HW acceleration-based architecture for network terminals. The demonstrator will be an IP (Intellectual property) core. The core should process protocol framing-deframing on the fly. The core should adapt to different protocols both in the SoC integration phase and even during running applications.

The project started at the beginning of 1999. Our current research activity is from the architectural level down to the silicon implementation. The project is running with the graduate school ECSEL, Switchcore (Dr. Kenny Ranerup), LME research of Ericsson (Dr. George Liu), and Freehand Communication (Harald Bergh).

Design for the SoC Bus - the SoC Network [37], [44]

(D Wiklund, D Liu)

The current available SoC integration methodology is based on either custom-designed glue logic or low-performance arbitration-based time-sharing buses. These solutions are far off the requirements from the infrastructure of modern communication systems (Base station, Gateway for example). Since the communication infrastructure is different from the infinite SW platform (SUN station for example), we have chances to attain real-time multiple-channel DMA-based communication on the chip level. The aim of the project is to demonstrate the network on a chip supporting multiple-dimensional multiple-DMA. The demonstrator will also show a methodology for short Time-To-Market of System integration.

We are investigating and defining the interface between cores on the chip, and we cooperate with the basic technology R&D at ERA (Dr. Anders Wass), Ericsson and FreeHand Communication (Harald Bergh). We have funding from the Swedish Foundation for Strategic Research (SSF) - the INTELECT program - as of January 2000 when the project started. Currently, we are developing the behavior C-model for the performance simulation and architecture optimization.

Accelerator-Based DSP Architecture

(M Olausson, D Liu)

The scale of general-purpose DSP processors is growing. Instruction sets become as complicated as a general purpose CPU, so that the hardware becomes very redundant. From one point of view, a general-purpose DSP processor can cover most functions. From another point of view, as jobs must be allocated on one device and scheduled according to the timing sequence, the performance of DSP processors can never be high, the number of MIPs can not be optimized, and the power consumption can never be low because of the centralized architecture.

Because communication industries are strong in Sweden we need to define a general DSP multiple processor model for different kinds of applications for communication industries. It could be a kind of accelerator and bus-based plug-in architecture. We define this kind of architecture as "Domain-Specific Processor Architecture".

The project formally started October 1st, 2000, when Mikael Olausson joined the group. The project is supported by Center for Industrial Information Technology at Linköping University (CENIIT) and the graduate school SCORE. We are working for the DSP platform for DSP accelerators. We are cooperating with FreeHand Communication (Harald Bergh) and we are getting more contact with Ericsson Mobile Communications in Lund (Erik Hertz).

Publications

[1]	K. C. Chen, N. T. Nuhfer, L. Porter and Q. Wahab: "High carbon concentration at the Silicondioxide-Siliconcarbide interface identified by electron energy loss spectroscopy", Applied Physics Letters 77, p. 2186, 2000.
[2]	A. Ellison, J. Zhang, W. Magnusson, A. Henry, Q. Wahab, J. Bergman, C. Hemmingsson, N. T. Son and E. Janzén: "Fast SiC epitaxial growth in a chimney reactor and HTCVD crystal growth development", Trans. Tech. Pub., Materials Science Forum 338-342, p. 131, 2000.
[3]	P. Hazucha, C. Svensson and S. A. Wender: "Cosmic-ray soft error rate characterization of a standard 0.6-um CMOS process", IEEE Journal of Solid-State Circuits, vol. 35, pp.1422-9, Oct. 2000.
[4]	P. Hazucha and C. Svensson: "Optimized test circuits for SER characterization of a manufacturing process", IEEE Journal of Solid-State Circuits, vol. 35, pp.142-8, Feb. 2000.
[5]	D. Jakonis, C. Svensson and C. Jansson: "Readout architectures for uncooled IR detector arrays", Sensors and Actuators A: Physical, vol. 84, no. 3, pp. 220-9, Sept. 2000.
[6]	R. Johnsson, Q. Wahab and S. Rudner: "Physical simulations for high frequency operation of microwave power transistors structure in 4H-SiC", Trans. Tech. Pub., Materials Science Forum 338-342, pp. 1263-6, 2000.
[7]	P. Larsson-Edefors: "Investigation on maximal throughput of a CMOS repeater chain", IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 47, no. 4, pp. 602-6, April 2000.
[8]	F. Mu and C. Svensson: "Pulsewidth control loop in high-speed CMOS clock buffers", IEEE Journal of Solid-State Circuits, vol. 35, no. 2, pp.134-41, Feb. 2000.
[9]	Q. Wahab, A. Ellison, C. Hallin, A. Henry and E. Janzén: "Influence of epitaxial growth and substrateinduced defects on the breakdown of 4H SiC Schottky diodes", Applied Physics Letters 76, p. 2725, 2000.
[10]	Q. Wahab, A. Ellison, C. Hallin, A. Henry and E. Janzén: "Study of breakdown limiting defects in 4H-SiC substrates and epilayers on the performance of high voltage Schottky diodes", Trans. Tech. Pub., Materials Science Forum 338-342, p.1175, 2000.
[11]	Q. Wahab, A. Ellison, J. Zhang, U. Forsberg and E. Janzén: "Designing, physical simulations and fabrication of high-voltage (3.85 kV) 4H-SiC Schottky rectifiers processed on hot-wall and high-temperature CVD grown films", Trans. Tech. Pub., Materials Science Forum 338-342, p. 1171, 2000.
[12]	S. Zangooie, P. O. A. Persson, L. Hultman, H. Arwin and Q. Wahab: "Microstructural and optical investigation of anodized 4H-SiC", Trans. Tech. Pub., Materials Science Forum 338-342, p. 537, 2000.
[13]	K. C. Chang, L. M. Porter, and Q. Wahab: "Chemical and electrical analysis at the silicon dioxide - 6H silicon carbide interface", submitted.
[14]	D. Eckerbert and P. Larsson-Edefors: "Cycle-true leakage current modeling for CMOS gates", accepted at 2001 IEEE Intl Symp. on Circuits and Systems.
[15]	D. Eckerbert and P. Larsson-Edefors: "Interconnect-driven short-circuit power modeling", submitted.
[16]	A. Ellison, C. Hemmingsson, B. Magnusson, A. Henry, N. T. Son, Q. Wahab and E. Janzén: "Development of a novel SiC crystal growth method: the HTCVD technique", Ultra Low Loss Power Devices 2000, Nara, Japan, in press.
[17]	K. Folkesson, J. -E. Eklund and C. Svensson: "Modeling of dynamic errors in algorithmic A/D converters", accepted at 2001 IEEE Intl Symp. on Circuits and Systems.
[18]	H. Eriksson, P. Larsson-Edefors and W. P. Marnane: "A regular parallel multiplier which utilizes multiple carry-propagate adders", accepted at 2001 IEEE Intl Symp. on Circuits and Systems.
[19]	H. Eriksson, P. Larsson-Edefors and A. Alvandpour: "A 2.8ns 30uW/MHz area-efficient 32-b Manchester carry-bypass adder", accepted at 2001 IEEE Intl Symp. on Circuits and Systems.
[20]	P. Hazucha and C. Svensson: "Impact of CMOS technology scaling on the atmospheric neutron soft error rate", IEEE Transactions on Nuclear Science, in press.
[21]	P. Hazucha and C. Svensson: "Cosmic ray neutron multiple-upset measurements in a 0.6 um CMOS process", IEEE Transactions on Nuclear Science, in press.
[22]	T. Henriksson, H. Eriksson and U. Nordqvist: "CRC-32 for 10 gigabit ethernet", submitted.
[23]	T. Henriksson, U. Nordqvist and D. Liu: "Job analysis and definition of a suitable assembly instruction set for protocol parsing", submitted.
[24]	Q. Wahab, E. Duranova, J. Zhang, L. D. Madsen and E. Janzén: "Improvements in the electrical performance of high-voltage 3.85 kV 4H-SiC Schottky diodes by hydrogen annealing", European Siliconcarbide and Related Materials Conf. 2000, in press.
[25]	P. Larsson-Edefors: "Professorer bland processorer", invited paper in Sommarutskick 2000 - läsvärda texter för dig som ska börja på Y, pp. 9-11, 2000.
[26]	P. Andersson, J. Alowersson, A. Edman, H. O. Johansson, T. Johansson, A. Lloyd, B. Roslund, L. -O. Svensson, P. Sundström, P. Tufvesson, K. Ranerup and C. Svensson: "A CMOS non-blocking 16x16 gigabit ethernet switch chip", Hot Chips 12 - Symp. on High Performance Chips at Stanford University, USA, Aug. 13-15 2000.
[27]	A. Alvandpour, P. Larsson-Edefors and C. Svensson: "GLMC: interconnect length estimation by growth-limited multifold clustering", Proc. of 2000 IEEE Intl Symp. on Circuits and Systems, Geneva, Switzerland, pp. V 465-8, May 28-31 2000.
[28]	G. Dermer and C. Svensson: "Time domain modeling of lossy interconnects", 2nd IMAPS Advanced Technology Workshop: Future Digital Interconnects over 1000 MHz, Austin, TX, USA, Jan. 17-18 2000.
[29]	M. Duppils and C. Svensson: "Low power mixed analog-digital signal processing," Proc. of IEEE Intl Symp.on Low Power Electronics and Design, Portofino Coast, Italy, pp. 61-6, July 2000.
[30]	D. Eckerbert, H. Eriksson, P. Larsson-Edefors and A. Edman: "An interconnect-driven design of a DFT processor", Proc. of IEEE Intl Symp. on Circuits and Systems, pp. V 569-72, Geneva, Switzerland, May 28-31 2000.
[31]	H. Eriksson and P. Larsson-Edefors: "Impact of voltage scaling on glitch power consumption", Proc. of the 10th Intl Workshop on Power and Timing Modeling, Optimization and Simulation, Göttingen, Germany, pp. 139-48, Sept. 13-15 2000.
[32]	J. Eriksson, N. Rorsman, H. Zirath, R. Johnsson, Q. Wahab and S. Rudner: "A comparison between physical simulations and experimental results in 4H-SiC MESFETs with non-constant doping in the channel and buffer layers", Proc. of the Third European Conf. on Silicon Carbide and Related Materials, Kloster Banz, Germany, Sept. 3-7 2000.
[33]	K. Folkesson, J. -E. Eklund, C. Svensson and A. Gustafsson: "A Matlab-based ADC model for RF system simulations", Proc. of Swedish National Symp. on GigaHertz Electronics, Göteborg, pp. 273-6, March 13-14 2000.
[34]	T. Henriksson, U. Nordqvist and D. Liu: "Configurable port processor increases flexibility in the protocol processing area", Proc. of COOL Chips III, Tokyo, Japan, April 24-25 2000.
[35]	T. Henriksson, U. Nordqvist and D. Liu: "Specification of a configurable general-purpose protocol processor", Proc. of CSNDSP 2000, Bournemouth, UK, July 18-20 2000.
[36]	R. Johnsson, Q. Wahab and S. Rudner: "Physical simulations of wide bandgap semiconductor microwave power transistors", Proc. of Swedish National Symp. on GigaHertz Electronics, Göteborg, pp. 387-90, March 13-14 2000.
[37]	D. Liu and D. Wiklund: "SoC bus", Presentation at EDA Träff 2000, Kista, Stockholm, April 2000.
[38]	R. Malmqvist, M. Danestig, S. Rudner and C. Svensson: "Analysis of narrow-band high performance recursive active MMIC filters for future adaptive on-chip radar receivers", Proc. of Swedish National Symp. on GigaHertz Electronics, Göteborg, pp. 137-40, March 13-14 2000.
[39]	R. Malmqvist, A. Gustafsson, M. Danestig, A. Ouacha, S. Hagelin and S. Rudner: "Noise and intermodulation properties of tunable recursive active MMIC filters for future adaptive on-chip radar receivers", Proc. of the 30th European Microwave Conf., Paris, France, pp. 1-4, Oct. 2-6 2000.
[40]	R. Malmqvist, A. Gustafsson, M. Danestig, A. Ouacha, S. Hagelin and S. Rudner: "Analysis of tunable narrow-band recursive active MMIC filters for future adaptive on-chip radar receivers", Proc. of the Asia Pacific Microwave Conf., Sydney, Australia, pp. 1073-6, Dec. 3-6 2000.
[41]	W. P. Marnane, S. J. Bellis, F. Murra, P. Larsson-Edefors and E. M. Popovici: "Bit-serial, bit interleaved processing - an area/power efficient architecture for SRAM FPGAs", 8th ACM Intl Symp. on Field-Programmable Gate Arrays, Monterey, CA, USA, Feb. 9-11 2000.
[42]	U. Nordqvist, T. Henriksson and D. Liu: "CRC Generation for Protocol Processing", Proc. of NORCHIP, Turku, Finland, Nov. 5-8 2000.
[43]	Q. Wahab, S. Rudner and E. Janzén: "Power Schottky rectifier and microwave transistors in 4H-SiC", Proc. of Intl Workshop for Semiconductor Devices, V. Kummar and S. K. Agarwal, Eds, Solid State Physics Lab., Lucknow Road, Delhi, Allied Publishers Ltd., New Delhi, p. 668, 2000.
[44]	D. Wiklund and D. Liu: "Switched interconnect for System-on-a-Chip designs", Proc. of the IP2000 Europe Conf., Edinburgh, UK, pp. 187-92, Oct. 23-24 2000.
[45]	M. Duppils: CMOS Mixed Analog/Digital Building Blocks for Signal Processing, Licentiate Thesis No 801, LiU-TEK-LIC-1999:59, March 2000.
[46]	P. Hazucha: Background Radiation and Soft Errors in CMOS Circuits, Dissertation No. 638, ISBN 91-7219-793-5, Sept. 2000.
[47]	M. Duppils: "Measurement on receiver building blocks", laboratory manual in TFFY71 High-speed electronics, undergraduate course, Nov. 2000.
[48]	H. Eriksson, D. Eckerbert and P. Larsson-Edefors: "VLSI design 2001", laboratory manual in TFFY90 VLSI design, undergraduate course, Nov. 2000.
[49]	D. Jakonis and P. Larsson-Edefors: "Semiconductor technology - Device measurements", laboratory manual in TFFY34 Semiconductor technology, undergraduate course, Sept. 2000.
[50]	P. Hazucha and P. Larsson-Edefors: "Semiconductor technology - Device simulations A", laboratory manual in TFFY34 Semiconductor technology, undergraduate course, Sept. 2000.
[51]	P. Hazucha and P. Larsson-Edefors: "Semiconductor technology - Device simulations B", laboratory manual in TFFY34 Semiconductor technology, undergraduate course, Sept. 2000.
[52]	T. Henriksson: "Design specification for the lab of TFYY35", laboratory manual in TFYY35 Introduction to design of DSP processors, undergraduate course, 2000.
[53]	P. Larsson-Edefors and C. Svensson: "Evaluation of an integrated circuit", compendium in TFFY94 Evaluation of an integrated circuit, undergraduate course, Sept. 2000.
[54]	P. Larsson-Edefors: "Semiconductor technology", compendium in TFFY34 Semiconductor technology, undergraduate course, Sept. 2000.
[55]	P. Larsson-Edefors: "VLSI design", collection of presentation transparencies in TFFY90 VLSI design, undergraduate course, May 2000.
[56]	D. Liu: "Introduction to design of embedded digital signal processors", compendium in TFYY35 Introduction to design of DSP processors, undergraduate course, 2000.
[57]	D. Liu: "Functional design methodology for DSP processors", compendium in TFYY35 Introduction to design of DSP processors, undergraduate course, 2000.
[58]	D. Liu: "High-speed electronics", collection of presentation transparencies in TFFY71 High-speed electronics, undergraduate course, Dec. 2000.
[59]	D. Liu: "Introduction to design of DSP processors", collection of presentation transparencies in TFYY35 Introduction to design of DSP processors, undergraduate course, Oct. 2000.
[60]	K. Folkesson: "Measurement laboratory guide", 2000.
[61]	C. Svensson and F. Mu: "Anordning och metod för att synkronisera data till en lokal klocka", Swedish patent SE9803100.