In the end of 1999, 18 people, of which ten are graduate students, are
engaged in research and teaching. Additionally, five external graduate
students (not employed at the group) are engaged.
Dake Liu gave one graduate course during 1999, DSP Processor Design
and Implementation Methodology, 5+5 p [50, 51, 52]. Dake Liu has also
given guest lectures in Advanced Issues in Computer Architecture,
a graduate course offered by the Dept. of Computer Science.
Per Larsson-Edefors has served as a member of the study board for the
master's programs in Computer Engineering and Science, Information Technology
and Computer Science, respectively, and is also responsible for the Physical
Electronics branch of study in the Applied Physics and Electrical Engineering
program. Furthermore, Per Larsson-Edefors has concluded the work on reforming
the undergraduate education in electronics at LiTH.
The research activities are mainly financed through external grants from several sources:
CMOS-Based Low-Power Electronics High-Frequency Wide-Bandgap Semiconductor Power Devices High-Speed CMOS Techniques Infrared Image Sensors Mixed-Signal Circuits Neutron-Induced Soft Errors in Electronics The Next Generation System-on-Chip
Christer Svensson is associate editor of IEEE Journal of Solid-State Circuits and has served in the program committees of the European Solid-State Circuits Conference (ESSCIRC) 1999 and the International Solid-State Circuits Conference (ISSCC) 2000 (European subcommittee). Per Larsson-Edefors served in the program committee of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 1999. Christer Svensson is also a member of the working group for Microelectronics within SSF. Per Larsson-Edefors was elected board member of the Dept. of Physics and Measurement Technology during 1999.
Christer Svensson has been on a sabbatical at Intel Corp., as of Aug. 1999. Per Larsson-Edefors has been acting head of the division in Christer Svensson's absence. Peter Hazucha has been with Intel Corp. during the summer of 1999. Dr. Liam Marnane, National Microelectronics Research Centre, Ireland, was a visiting scientist with the Electronic devices division Aug. 1999 - Dec. 1999.
In summary, during 1999 the group has published 13 journal papers and 30 papers in national and international conferences. Two patent applications have been filed.
There are two main reasons for the large research momentum in the field
of low-power electronics:
The first reason relates to energy consumption reduction, but reducing energy consumption is equivalent to reducing average power consumption as long as a reduced performance is not compensated for by an extended operation time during which power is consumed. Increasing battery life-time in portable applications today is the main motivation for energy consumption reduction, but in a longer term and on a larger scale, the energy consumed by electronic equipment has to be reduced to ensure a sustainable standard of living for mankind.
The second reason for reducing power consumption is related to problems arising from the high level of integration and the cost associated to the solutions to these problems. The heat dissipation from a microprocessor chip consuming more than 10 W imposes huge problems in cooling the chip; hence, the packaging is very expensive. Moreover, apart from the degraded performance that comes with increased chip temperature, the chip material deteriorates more rapidly in high temperatures than in low, which manifests itself in reduced reliability.
The phenomena of particular interest are short circuits, Miller (mutual) capacitances and undesired signal transitions (glitches). Mature as well as preliminary results show very promising qualities, and the goal of creating both understanding and estimation methods have been accomplished in several critical domains. For example, we have developed a method for extracting short-circuit power consumption and also managed to quantify the impact of Miller capacitance on power consumption.
When running simulations at RT level, almost only input and output signals are available. A viable model for the power consumption is the linear regression model, where transitions at the inputs and outputs are weighed against power consumption. To improve the precision of this model, the input/output vectors are stratified into several classes, each of which has its own set of power consumption parameters. Currently in this project, part of our work is devoted to investigating methods for improving the linear regression model . Key issues involve deciding stratification parameters and introduction of physical interaction between RTL components. Also, work on peak power estimation for use at RT level is underway.
At application-specific levels we have three sub projects running:
At circuit level we have been active in three different sub projects:
One sub project, which has been pursued recently, is to trade off power for noise. Here, the key is to concurrently analyze application and circuit, to identify parts where an increased amount of inaccuracy can be accepted at the benefit of power reduction [26, 27]. The second sub project comprises a low-power high-performance DFT processor, which is under development. A sub set of the processor, including a full processing element, has been designed in a 0.35-um CMOS process and has arrived from fabrication. This design project has the explicit goal of combining a number of power-saving design methods within a novel implementation structure . Low-power implementations targeted for FPGAs is the third project. Here, the experience of circuit design has aided us in reconfiguring an FPGA, such that power can be reduced. The power-reduction technique is based on a transformation of arithmetic implementations into bit-interleaved structures, for which SRAM cells can be used as storage elements . The formal foundation of the transformations was given in .
A very power consuming part of large chips is long interconnects or buses. Low-swing implementations usually require additional hardware and large design efforts. We have developed a new low-power driver-receiver circuit for long interconnects  as well as a new low-power multi-threshold receiver . Aiming for high performance (speed) usually requires extensive partitioning of logic gates, which prohibits good characteristics in power and area. High fan-in precharged gates can extend their complexity into two different directions:
The gate can contain an evaluation network, which has a transistor structure with little degree of stacking but many parallel transistors. Then leakage is a problem (which will get worse in the future) as the keeper transistor under some conditions needs to draw a large amount of current to replenish the charge of the dynamic node. We have developed a low-power circuit technique for designing keepers for high fan-in precharge gates of this type (parallel evaluation transistors) .
The other gate type is the one containing many series transistors sitting in a stack, thus leading to very low speed. We have developed a new sensing element, that can cut down the delay and save power for high fan-in precharge gates of this type (stacked evaluation transistors) .
Datapath components are key to all electronics design, and pose design difficulties as they require a tight inter-relation between the algorithm of the operation and the circuit structure to function efficiently. We are currently investigating new circuit solutions in known parallel adder and multiplier micro-architectures. By using a new transistor solution for a Manchester carry chain, we have been able to reduce the delay of a 32-bit adder from the 35ns of a conventional one to 5ns; and a saving in power was also effected .
During 1999 we have performed numerical drift-diffusion simulations using a commercial program, Medici, from Avant Corporation. We have utilized the most recently published model parameters for 4H-SiC to obtain the closest agreement with experimental data. Our simulations showed that the selection of buffer layer doping and thickness affects the transistors drain characteristics significantly. The semi-insulating substrate properties strongly affect the transistor performance if the buffer layer is too thin and low doped. On the other hand, the use of a thick, highly doped buffer layer reduces the drain current significantly. When operating at a drain voltage of 130 V and gate bias of +2 V, the temperature in the channel region can reach 636 K for a device with a 50-um thick semi-insulating substrate connected to a perfect heat sink.
The chip interfaces have become the most important bottleneck to further increase computing capacity. It is simply not possible to deliver enough input data to the processor to fully utilize its capacity. This is clearly demonstrated by the fact that the on-chip clock frequencies now approach 1 GHz, whereas the clock frequency on the boards in most cases is limited to 200 MHz and below.
The increasing processing capacity of digital processors has also lead to the trend to perform more and more tasks digitally. Still, for the highest speeds or for weak signals, analog processing is necessary. In fact, also in the case of strong signals, as in transmitters, analog processing is needed. Analog signal processing is, of course, also necessary when converting signals between the analog and the digital domain. Typical applications are the input interfaces to analog communication channels, such as wireless channels, long copper wires at high speed and optical fibers.
It is the objective of this project to develop techniques which better solve actual problems in the above mentioned areas than the solutions of today.
Several years of work on very high throughput digital circuits was presented as an invited talk at Symposium on VLSI .
The ultimate limit for the data rate between chips is given by the properties of the transport medium, in this case the printed circuit board. We have therefore developed a new time domain model for printed circuit boards, which allow accurate analysis of signal transfer and accurate prediction of maximum data rates . (This work was performed at Intel Corp., OR, USA). Further studies will include receiver architectures for very high data rates between chips (~10 Gb/s). Concerning the optical alternative to electrical, we performed a comparison study demonstrating that electrical interconnect is preferable at short distances .
Another application for high-speed interfaces occurs in connection to the fast-developing fiber communication. We have initiated a study of the possibility to integrate the photodiode interface in CMOS, by the enrollment of Ph. D. student Håkan Bengtson, halftime employee of Mitel Semiconductors.
In close collaboration with the Defence Research Establishment (FOA), we have initiated a study of the possibilities to design high quality, tunable filters /low noise amplifiers utilizing the principle of recursive active filters. We have theoretically investigated how these filter properties depend on filter topology and amplifier design [7, 8, 34, 35, 36]. Starting from the performance requirements of a typical radar receiver we have used our analytical model to find a suitable filter topology. A cascaded second-order recursive active filter based on HEMT amplifiers was found to be a promising candidate to achieve the adequate performance. We are currently studying the practical MMIC implementation of these filters using standard foundry GaAs processes.
In the InfraRed (IR) project we were responsible for the investigation and development of suitable readout electronics for an IR sensor based on a microbolometer focal plane array. For this purpose a readout circuit connected to an array of novel high-resolution A/D-converters was developed. This work has been internationally recognized and has produced several publications over the years. The readout operation and performance has been verified with detectors from both Acreo and Defence Science and Technology Organisation in Australia. The IR consortium will continue to use this readout for development and evaluation of new higher performance detector materials, until the end of year 2000, when this consortium is planned to terminate.
During 1999 a fundamental noise analysis for different degrees of parallelism has been performed, such that an optimum choice of readout structure can be made with respect to noise. This work has resulted in a manuscript for Sensors and Actuators .
The dominating cosmic radiation in the atmosphere (including ground) is neutron radiation. The neutron flux gives rise to so-called single event upsets, or soft errors, in electronics. As the stored charge in each logical node decreases with decreased dimensions and voltage, the soft error rate will increase. Our objective is to develop methods for the investigation and prediction of these phenomena.
We have performed measurements on real chips in environments with high neutron flux, at high altitudes (in airplanes) and in artificial neutron flux (The Svedberg Laboratory in Uppsala and Los Alamos Laboratories in New Mexico). We also developed a special test chip for a systematic characterization of the fabrication process [3, 30], and performed process characterization of single event upsets with this chip . We also performed measurements of multiple-bit upsets in SRAMs .
The project is divided into three sub projects:
|||S J Bellis, W P Marnane and P Larsson-Edefors: "Bit Serial, MSB First Processing Units", Intl J. of Electronics, vol. 86, no. 6, pp. 723-38, June 1999.|
|||E Berglind, L Thylen, B Jaskorzynska and C Svensson: "A Comparison of Dissipated Power and Signal-To-Noise Ratios in Electrical and Optical Interconnects", J. of Lightwave Technology, vol. 17, no. 1, pp. 68-73, Jan. 1999.|
|||P Hazucha and C Svensson: "Optimized Test Circuits for SER Characterization of a Manufacturing Process", to be published in IEEE J. Solid-State Circuits, Feb. 2000.|
|||D Jakonis, C Svensson and C Jansson: "Readout Architectures for Uncooled IR Detector Arrays", to be published in Sensors and Actuators A.|
|||K Johansson, M Ohlsson, N Ohlsson, J Blomgren and P-U Renberg: "Neutron Induced Single-Word Multiple-Bit Upset in SRAM", IEEE Trans. on Nuclear Science, Dec. 1999.|
|||P Larsson-Edefors: "Investigation on Maximal Throughput of a CMOS Repeater Chain", to be published in IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications.|
|||R Malmqvist, M Danestig, S Rudner and C Svensson: "Some Limiting Factors for the Noise Optimization of Recursive Active Microwave Integrated Filters", Microwave and Optical Technology Letters, vol. 22, no. 3, pp. 151-7, Aug. 1999.|
|||R Malmqvist, M Danestig, S Rudner and C Svensson: "Theoretical Analysis of Sensitivity and Q-Value for Recursive Active Microwave Integrated Filters", IEE Proceedings - Microwaves, Antennas and Propagation, vol. 146, no. 4, pp. 247-52, Aug. 1999.|
|||F Mu and C Svensson: "A Layout-Based Schematic Method for Very High-Speed CMOS Cell Design", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 1, pp. 144-8, March 1999.|
|||F Mu and C Svensson: "Analysis and Optimization of a Uniform Long Wire and Driver", IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 46, no. 9, pp. 1086-1100, Sept. 1999.|
|||F Mu and C Svensson: "Vector Transfer by Self-Tested Self-Synchronization for Parallel Systems", IEEE Trans. on Parallel and Distributed Systems, vol. 10, no. 8, pp. 769-80, Aug. 1999.|
|||F Mu, A Edman and C Svensson: "Digital Multiphase Clock/Pattern Generator", IEEE J. of Solid-State Circuits, vol. 34, no. 2, pp. 182-91, Feb. 1999.|
|||J Yuan and C Svensson: "Multigigahertz TSPC Circuits in Deep Submicron CMOS", Physica Scripta, T79, pp. 283-6, 1999.|
|||P Larsson-Edefors: "Professorer bland processorer", invited paper in Sommarutskick 1999 - läsvärda texter för dig som ska börja på Y, pp. 12-3, 1999.|
|||A Alvandpour, P Larsson-Edefors and C Svensson: "A Leakage-Tolerant Multi-Phase Keeper for Wide Domino Circuits", Proc. of the 6th IEEE Intl Conf. on Electronics, Circuits and Systems, vol. I, pp. 209-12, Pafos (Cyprus), Greece, Sept. 5-8 1999.|
|||A Alvandpour, P Larsson-Edefors and C Svensson: "GLMC: Interconnect Length Estimation by Growth-Limited Multifold Clustering", to be presented at IEEE Intl Symp. on Circuits and Systems, Geneva, Switzerland, 2000.|
|||G Dermer and C Svensson: "Time Domain Modeling of Lossy Interconnects", to be presented at 2nd IMAPS Advanced Technology Workshop: Future Digital Interconnects over 1,000 MHz, Austin, TX, USA, Jan. 17-18 2000.|
|||M Duppils, J-E Eklund and C Svensson: "A Novel Mixed Analog/Digital MAC Unit Implemented with SC Technique Suitable for Fully Programmable Narrow-Band FIR Filter Applications", Proc. of IEEE Intl Conf. on Electronics, Circuits and Systems, pp. 1197-200, Pafos (Cyprus), Greece, Sept. 5-8 1999.|
|||M Duppils, J-E Eklund and C Svensson: "A Study of the Non-Ideal Properties of Sample-and-Hold Circuits with Respect to the Analog Bandwidth", Proc. of the 3rd IEE Intl Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications, pp. 119-21, Glasgow, UK, July 27-28 1999.|
|||M Duppils, J-E Eklund and C Svensson: "Realization of Fully Programmable Narrow-Band FIR Filters with SC Technique", Proc. of Midwest Symp. on Circuits and Systems, Las Cruces, NM, USA, Aug. 1999.|
|||M Duppils: "A Mixed Analog/Digital Multiply-Accumulate Unit Suitable for Implementation with CMOS Technology", Proc. of the 2nd Conf. on Computer Science and Systems Engineering in Linköping, pp. 101-7, Norrköping, Sweden, Oct. 21-22 1999.|
|||D Eckerbert, H Eriksson, P Larsson-Edefors and A Edman: "An Interconnect-Driven Design of a DFT Processor", to be presented at IEEE Intl Symp. on Circuits and Systems, Geneva, Switzerland, 2000.|
|||J-E Eklund and F Gustafsson: "Digital Offset Compensation of Time-Interleaved ADC Using Random Chopper Sampling", to be presented at IEEE Intl Symp. on Circuits and Systems, Geneva, Switzerland, 2000.|
|||J-E Eklund: "Randomization for Error Identification in ADC", to be presented at GigaHertz 2000.|
|||J-E Eklund: "Robust ADC Concept for Integrated CMOS Systems", Proc. of the 3rd IEE Intl Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications, pp. 126-9, Glasgow, UK, July 27-28 1999.|
|||H Eriksson, A Edman and P Larsson-Edefors: "Multiplexer-Based Low-Power Phase Accumulator", Proc. of RadioVetenskap och Kommunikation 99, pp. 323-7, Karlskrona, Sweden, June 14-17 1999.|
|||H Eriksson, P Larsson-Edefors and A Edman: "Using Clock Division to Reduce Power Consumption", Proc. of the 9th Intl Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 211-20, Kos Island, Greece, Oct. 6-8 1999|
|||J Eriksson, N Rorsman, H Zirath, Q Wahab and S Rudner: "SiC Microwave Power Transistors", Proc. of RadioVetenskap och Kommunikation 99, pp. 216-20, Karlskrona, Sweden, June 14-17 1999.|
|||K Folkesson, J-E Eklund, C Svensson and A Gustafsson, "A Matlab-Based ADC Model for RF System Simulations", to be presented at GigaHertz 2000.|
|||P Hazucha and C Svensson: "Circuit Technique for Accurate Soft Error Rate Measurements", Proc. of the 25th European Solid-State Circuits Conf., pp. 190-3, Duisburg, Germany, Sept. 21-23 1999.|
|||P Hazucha and C Svensson: "Experiment-Based Methodology for Modeling of SER in Modern CMOS Technologies", Proc. of the 2nd Conf. on Computer Science and Systems Engineering in Linköping, pp. 93-100, Norrköping, Sweden, Oct. 21-22 1999.|
|||R Jonsson, Q Wahab and S Rudner: "Physical Simulations on the Operation of 4H-SiC Microwave Power Transistors", Proc. of the Intl Conf. on Silicon Carbide and Related Materials, Research Triangle Park, NC, USA, Oct. 10-15 1999.|
|||D Liu, U Nordqvist and C Svensson: "Configuration Based Architecture for High Speed and General Purpose Protocol Processing", Proc. of IEEE Workshop on Signal Processing Systems, Taipei, Taiwan, ROC, Oct. 20-22 1999.|
|||R Malmqvist, M Danestig, S Rudner and C Svensson: "Analysis of Intermodulation and Noise Performance for Recursive Active Microwave Integrated Filters", Proc. of the 29th European Microwave Conf., pp. 60-3, Munich, Germany, Oct. 4-8 1999.|
|||R Malmqvist, M Danestig, S Rudner and C Svensson: "Estimation of Spurious-Free Dynamic Range for Recursive Active Microwave Integrated Filters", Proc. of the Asia Pacific Microwave Conf., Singapore, Nov. 30 - Dec. 3 1999.|
|||R Malmqvist, A Gustafsson, M Danestig, S Rudner and C Svensson: "Noise and Temperature Behavior of Tunable Recursive Active MMIC-Filters for On-Chip Microwave Receivers", Proc. of RadioVetenskap och Kommunikation 99, pp. 232-6, Karlskrona, Sweden, June 14-17 1999.|
|||W P Marnane, S J Bellis, F Murra, P Larsson-Edefors and E M Popovici: "Bit-Serial, Bit Interleaved Processing - An Area/Power Efficient Architecture for SRAM FPGAs", to be presented at 8th ACM Intl Symp. on Field-Programmable Gate Arrays, Monterey, CA, USA, Feb. 2000.|
|||F Mu and C Svensson: "A 750 Mb/s 0.6 um CMOS Two-Phase Input Port Using Self-Tested Self-Synchronization", IEEE Intl Solid-State Circuits Conf., Digest of Technical Papers, pp. 178-9, San Francisco, CA, USA, Feb. 15-17 1999.|
|||F Mu and C Svensson: "High Speed Interface for System-on-Chip Design by Self-Tested Self-Synchronization", Proc. of IEEE Intl Symp. on Circuits and Systems, vol. 2, pp. 516-9, Orlando, FL, USA, May 30 - June 2 1999.|
|||F Mu and C Svensson: "High Speed Multistage CMOS Clock Buffers with Pulse Width Control Loop", Proc. of IEEE Intl Symp. on Circuits and Systems, vol. 2, pp. 541-4, Orlando, FL, USA, May 30 - June 2 1999.|
|||F Mu and C Svensson: "Methodology of Layout Based Schematic and Its Usage in Efficient High Performance CMOS Design", Proc. of IEEE Intl Symp. on Circuits and Systems, vol. 6, pp. 254-7, Orlando, FL, USA, May 30 - June 2 1999.|
|||C Svensson: "High Speed Electronics Interfacing Fiber Networks", Proc. of the 25th European Solid-State Circuits Conf., p. 21, Duisburg, Germany, Sept. 21-23 1999.|
|||C Svensson and A Edman: "10-100 Gb/s Throughput CMOS Techniques", 1999 Symp. on VLSI Circuits, Digest of Technical papers, pp. 65-8, Kyoto, Japan, June 17-19 1999.|
|||Q Wahab, S Rudner and E Janzén: "Power Schottky Rectifiers and Microwave Transistors in 4H-SiC", Proc. of the 10th Intl Workshop on the Physics of Semiconductor Devices, New Delhi, India, Dec. 14-18 1999.|
|||M Danestig: Microwave Filters and Receivers for Adaptive Radar, Linköping studies in science and technology, Licentiate Thesis 785, Sept. 1999.|
|||P Hazucha: Neutron-Induced Soft Errors in CMOS Circuits, Linköping studies in science and technology, Licentiate thesis 768, Sept. 1999.|
|||R Malmqvist: Theoretical Analysis of Recursive Active Microwave Integrated Filters, Linköping studies in science and technology, Licentiate thesis 777, Sept. 1999|
|||A Alvandpour: Power Estimation and Low Power CMOS Circuit Techniques, Linköping studies in science and technology, Dissertation 587, ISBN 91-7219-503-7, June 1999.|
|||F Mu: Design of Large Scale and High Speed Integrated Systems, Linköping studies in science and technology, Dissertation 564, ISBN 91-7219-414-6, Feb. 1999.|
|||D Liu: "A Simplified FIR IIR Core", compendium in Digital signal processor design and implementation methodology, graduate course, 1999.|
|||D Liu: "Design Methodology for DSP Processors, Part One: Functional Design", compendium in Digital signal processor design and implementation methodology, graduate course, 1999.|
|||D Liu: "Design Methodology for DSP Processors, Part Two: ASIC Implementation", compendium in Digital signal processor design and implementation methodology, graduate course, 1999.|
|||M Duppils: "Measurement on Receiver Building Blocks", laboratory manual in TFFY71 High-speed electronics, undergraduate course, Oct. 1999.|
|||D Eckerbert, H Eriksson, et.al.: "VLSI Design 2000", laboratory manual in TFFY90 VLSI design, undergraduate course, Dec. 1999.|
|||P Larsson-Edefors and C Svensson: "Evaluation of an Integrated Circuit", compendium in TFFY94 Evaluation of an integrated circuit, undergraduate course, Oct. 1999.|
|||P Larsson-Edefors: "Semiconductor Technology", compendium in TFFY34 Semiconductor technology, undergraduate course, Oct. 1999.|
|||P Larsson-Edefors: "VLSI Design", collection of presentation transparencies in TFFY90 VLSI design, undergraduate course, May 1999.|
|||P Larsson-Edefors, P Hazucha, et.al.: "Semiconductor Technology - Laboratory Exercises", laboratory manual in TFFY34 Semiconductor technology, undergraduate course, Oct. 1999.|
|||D Liu: "High-Speed Electronics", collection of presentation transparencies in TFFY71 High-speed electronics, undergraduate course, Dec. 1999.|
|||R Malmqvist: "Characterization of a Low Noise Amplifier", laboratory manual in TFFY71 High-speed electronics, undergraduate course, Oct. 1999.|
|||A Alvandpour, P Larsson-Edefors and C Svensson: "A High-Speed, Low-Power Interconnect Architecture", manuscript.|
|||A Alvandpour, P Larsson-Edefors and C Svensson: "A Low-Power, High-Speed and Robust Clocked Driver-Receiver Circuit for Long On-Chip Interconnects", manuscript.|
|||A Alvandpour, P Larsson-Edefors and C Svensson: "Design-Sensitive Interconnection Length Estimation", submitted.|
|||A Alvandpour, P Larsson-Edefors and C Svensson: "Fast and Energy-Efficient Sensing Elements for High Fan-In Domino Gates", manuscript.|
|||R Arvidsson, M Duppils and J-E Eklund: "Switched Capacitors", Swedish patent application no. 902253-5.|
|||D Eckerbert, P Larsson-Edefors, and A Alvandpour: "Circuit-Level Considerations for Power Macro Modeling", manuscript.|
|||J-E Eklund and F Gustafsson: "Offsetkompensering i analog-till-digitalomvandlare", Swedish patent application no. 9901233-8.|
|||J-E Eklund and C Svensson: "Influence of Metastability Errors on SNR in Successive-Approximation A/D Converters", manuscript.|
|||H Eriksson, A Alvandpour and P Larsson-Edefors: "A Sensing-Element Approach to High-Speed Manchester Adders", submitted.|
|||T Henriksson and D Liu: "Early Partitioning of the Control for a General Purpose Protocol Processor", manuscript.|
|||D Liu and A Arvidsson: "SCI, SPI and Serial ADC Interface Compatible Core", manuscript.|